SSE2

From MediaCoderWiki

SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction, Multiple Data) instruction sets. SSE2 was first introduced by Intel with the initial version of the Pentium 4 in 2001. It extends the earlier SSE instruction set, and is intended to fully supplant MMX. Intel extended SSE2 to create SSE3 in 2004. SSE2 added 144 new instructions to SSE, which has 70 instructions. Rival chip-maker AMD added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of AMD64 64-bit CPUs in 2003.

Changes

SSE2 extends MMX instructions to operate on XMM registers, allowing the programmer to completely avoid the eight 64-bit MMX registers "aliased" on the original IA-32 floating point register stack. This permits mixing integer SIMD and scalar floating point operations without the mode switching required between MMX and x87 floating point operations. However, this is over-shadowed by the value of being able to perform MMX operations on the wider SSE registers.

Other SSE2 extensions include a set of cache-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information, and a sophisticated complement of numeric format conversion instructions.

AMD's implementation of SSE2 on the AMD64 (x86-64) platform includes an additional eight registers, doubling the total number to 16 (XMM0 through XMM15). These additional registers are only visible when running in 64-bit mode. Intel adopted these additional registers as part of their support for x86-64 architecture (or in Intel's parlance, "Intel 64") in 2004.

CPUs supporting SSE2

• AMD K8-based CPUs (Athlon 64, Sempron 64, Turion 64, etc)
• AMD Phenom CPUs
• Intel NetBurst-based CPUs (Pentium 4, Xeon, Celeron, Celeron D, etc)
• Intel Pentium M and Celeron M
• Intel Core-based CPUs (Core Duo, Core Solo, etc)
• Intel Core 2-based CPUs (Core 2 Duo, Core 2 Quad, etc)
• Intel Atom
• Transmeta Efficeon
• VIA C7
• VIA Nano

Notable IA-32 CPUs not supporting SSE2

SSE2 is an extension of the IA-32 architecture. Therefore any architecture that does not support IA-32 does not support SSE2. x86-64 CPUs all implement IA-32. All known x86-64 CPUs also implement SSE2. Since IA-32 predates SSE2, early IA-32 CPUs did not implement it. SSE2 and the other SIMD instruction sets were intended primarily to improve CPU support for realtime graphics, notably gaming. A CPU that is not marketed for this purpose or that has an alternative SIMD instruction set has no need for SSE2.

The following CPUs implemented IA-32 after SSE2 was developed, but did not implement SSE2:

• AMD CPUs prior to Athlon 64, including all Socket A-based CPUs
• Intel CPUs prior to Pentium 4
• Via C3
• Transmeta Crusoe