MMX
From MediaCoderWiki
MMX is a single instruction, multiple data (SIMD) instruction set designed by Intel, introduced in 1997 in their Pentium line of microprocessors, designated as "Pentium with MMX Technology". It developed out of a similar unit first introduced on the Intel i860. MMX is a processor supplementary capability that is supported on recent IA-32 processors by Intel and other vendors.
Intel's competitor AMD enhanced Intel's MMX with the 3DNow! instruction set to work with floating-point numbers. Intel would follow AMD's lead on floating-point math and created the SSE extension two years later.
Technical details
MMX added eight new registers to the architecture, known as MM0 through MM7 (henceforth referred to as MMn). In reality, these new "registers" were just aliases for the existing x87 FPU stack registers. Hence, anything that was done to the floating point stack would also affect the MMX registers. Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible.
Each of the MMn registers holds a 64-bit integer. However, one of the main concepts of the MMX instruction set is the concept of packed data types, which means instead of using the whole register for a single 64-bit integer (quadword), two 32-bit integers (doubleword), four 16-bit integers (word) or eight 8-bit integers (byte) may be used.
To simplify the design and to avoid modifying the operating system to preserve additional state through context switches, MMX re-uses the existing eight IA-32 FPU registers. This made it difficult to work with floating point and SIMD data at the same time. To maximize performance, programmers must use the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible.
Also because the MMX's 64-bit MMn registers are aliased to the FPU stack, and each of the stack registers is 80 bits wide, the upper 16 bits of the stack registers go unused in MMX, and these bits are set to all ones, which makes it look like NaNs or infinities in the floating point view. This makes it easier to tell whether the work is on floating point data or MMX data.
Another problem for MMX is that it only provides integer operations. Each of the eight 64-bit MMX vector registers, aliased on the eight existing floating point registers, could represent two 32-bit integers, four 16-bit short integers, or eight 8-bit bytes. When originally developed in the i860, the use of vectored-integer math made sense (both 2D and 3D setup required it), but as the systems moved to using graphics cards that did this, MMX fell out of favor and vectored-floating point became much more important. On the other hand, its new arithmetic operations did include saturation arithmetic operations, which could significantly speed up some digital signal processing applications.
Successor
Intel addressed the shortcomings of the MMX technology through SSE, a greatly expanded set of SIMD instructions with 32-bit floating point support and an additional set of 128-bit vector registers that made it easy to perform SIMD and FPU operations at the same time. SSE was in turn expanded with SSE2, which also extended MMX instructions so they can operate on 128-bit XMM registers (later SSE extensions would still support operating integer data on MMX registers because the new SSE registers require OS support, until SSE4, which ended this support) and recently with SSE4.2, introduced in the Intel Core microarchitecture. Support for any of these later instruction sets implies support for MMX.
